TXEIM=Val_0x0, MSTIM=Val_0x0, RXOIM=Val_0x0, RXUIM=Val_0x0, RXFIM=Val_0x0, TXOIM=Val_0x0
Interrupt Mask Register
| TXEIM | Transmit FIFO Empty Interrupt Mask. 0 (Val_0x0): Transmit FIFO Empty interrupt is masked 1 (Val_0x1): Transmit FIFO Empty interrupt is not masked |
| TXOIM | Transmit FIFO Overflow Interrupt Mask. 0 (Val_0x0): Transmit FIFO Overflow interrupt is masked 1 (Val_0x1): Transmit FIFO Overflow interrupt is not masked |
| RXUIM | Receive FIFO Underflow Interrupt Mask. 0 (Val_0x0): Receive FIFO Underflow interrupt is masked 1 (Val_0x1): Receive FIFO Underflow interrupt is not masked |
| RXOIM | Receive FIFO Overflow Interrupt Mask. 0 (Val_0x0): Receive FIFO Overflow interrupt is masked 1 (Val_0x1): Receive FIFO Overflow interrupt is not masked |
| RXFIM | Receive FIFO Full Interrupt Mask. 0 (Val_0x0): Receive FIFO Full interrupt is masked 1 (Val_0x1): Receive FIFO Full interrupt is not masked |
| MSTIM | Multi-Master Contention Interrupt Mask. This bit is not present if the SPI is configured as a serial master device. 0 (Val_0x0): Multi-Master Contention interrupt is masked 1 (Val_0x1): Multi-Master Contention interrupt is not masked |